View 1698_850210.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ltc1698 1698f applicatio s u descriptio u features typical applicatio u the ltc ? 1698 is a precision secondary-side forward converter controller that synchronously drives external n-channel mosfets. it is designed for use with the lt ? 3781 primary-side synchronous forward converter controller to create a completely isolated power supply. the lt3781 synchronizes the ltc1698 through a small pulse transformer and the ltc1698 drives a feedback optocoupler to close the feedback loop. output accuracy of 0.8% and high efficiency over a wide range of load currents are obtained. the ltc1698 provides accurate secondary-side current limit using an external current sense resistor. the input voltage at the margin pin provides 5% output voltage adjustment. a power good flag and overvoltage input are provided to ensure proper power supply conditions. an auxiliary 3.3v logic supply is included that supplies up to 10ma of output current. isolated secondary synchronous rectifier controller n high efficiency over wide load current range n 0.8% output voltage accuracy n dual n-channel mosfet synchronous drivers n pulse transformer synchronization n optocoupler feedback driver n programmable current limit protection n 5% margin output voltage adjustment n adjustable overvoltage fault protection n power good flag n auxiliary 3.3v logic supply n available in 16-lead ssop and so packages n 48v input isolated dc/dc converters n isolated telecommunication power systems n distributed power step-down converters n industrial control systems n automotive and heavy equipment figure 1. simplified 2-transistor isolated forward converter , ltc and lt are registered trademarks of linear technology corporation. + + cg v dd pwrgd ltc1698 pgnd gnd 28 c fb c c c cilm r c v out r cilm r2 r5 r4 r1 l1 6 13 9 7 14 c out 110 q4 v in 36v to 72v q3 t1 q1 d1 q2 r prisen t2 fg 16 i sns r secsen 12 i snsgnd 11 sync v fb v comp v aux i comp ovpin margin v margin o.1 f 1681 f01 v aux 3.3v 10ma 15 optodrv please refer to figure 12 in the typical applications section for the complete 3.3v/15a application schematic 5 34 r sync r k r e isolation boundary r f ref v fb sg tg bg lt3781 v c c sync c k c f v dd bias c sg + d2
2 ltc1698 1698f (note 1) v dd , pwrgd ....................................................... 13.2v input voltage margin, v fb , ovpin, i snsgnd , i sns ... C 0.3v to 5.3v sync ..................................................... C 14v to 14v output voltage v comp , i comp (note 2) ......................... C 0.3v to 5.3v power dissipation .............................................. 500mw operating temperature range ltc1698e (note 3) ............................ C 40 c to 85 c ltc1698i ........................................... C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c absolute m axi m u m ratings w ww u package/order i n for m atio n w u u order part number ltc1698egn ltc1698es ltc1698ign ltc1698is t jmax = 125 c, q ja = 130 c/w (gn) t jmax = 125 c, q ja = 110 c/w (so) gn package 16-lead plastic ssop s package 16-lead plastic so 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 v dd cg pgnd gnd optodrv v comp margin v fb fg sync v aux i comp i sns i snsgnd pwrgd ovpin the l indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dd = 8v, unless otherwise noted. (note 4) electrical characteristics consult ltc marketing for parts specified with wider operating temperature ranges. symbol parameter conditions min typ max units v dd supply voltage l 6 8 12.6 v v uvlo undervoltage lockout 4v i vdd v dd supply current v fb , ovpin, v isns , v isnsgnd = 0v, c fg = c cg = 1000pf, c vaux = 0.1 m f, v sync = 0v l 1.8 4 ma f sync = 100khz (note 5) 5.0 ma margin and error amplifier v fb feedback voltage margin = open, v comp = 1v (note 7) 1.223 1.233 1.243 v l 1.215 1.233 1.251 v i vfb feedback input current v fb = 1.233v l 0.05 1 m a v margin margin voltage margin = open 1.65 v r margin margin input resistance 16.5 k w d v fb feedback voltage adjustment v margin = 3.3v l 456 % v margin = 0v l C6 C5 C4 % g err error amplifier open-loop dc gain v comp = 0.8v to 1.2v, load = 2k w , 100pf l 65 90 db bw err error amplifier unity-gain bandwidth no load (note 6) 2 mhz v clamp error amplifier output clamp voltage v fb = 0v 2 v i vcomp error amplifier source current v fb = 0v l C25 C10 ma error amplifier sink current v fb = 5v, v comp = 1.233v l 37 ma optodrv g opto opto driver dc gain ovpin, v isns , v isnsgnd = 0v l 4.75 5 5.25 v/v bw opto opto driver unity-gain bandwidth no load (note 6) 1 mhz v optohigh opto driver output high voltage v fb , ovpin, v isnsgnd = 0v, v isns = C 50mv, i optodrv = C10ma l 45 v i optosc opto driver output short-circuit current ovpin, v isnsgnd , v isns = 0v, v fb = 1.233v l C50 C25 C10 ma gn part marking 1698 1698i
3 ltc1698 1698f the l indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dd = 8v, unless otherwise noted. (note 4) electrical characteristics note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. all voltages refer to gnd. note 2: the ltc1698 incorporates a 5v linear regulator to power internal circuitry. driving these pins above 5.3v may cause excessive current flow. guaranteed by design and not subject to test. note 3: the ltc1698e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C 40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. for guaranteed performance to specifications over the C40 c to 85 c range, the ltc1698i is available. note 4: all currents into device pins are positive; all currents out of the device pins are negative. all voltages are referenced to ground unless otherwise specified. for applications with v dd < 7v, refer to the typical performance characteristics. note 5: supply current in active operation is dominated by the current needed to charge and discharge the external fet gates. this will vary with the ltc1698 operating frequency, supply voltage and the external fets used. note 6: this parameter is guaranteed by correlation and is not tested. note 7: v fb is tested in an op amp feedback loop which servos v fb to the internal bandgap voltage. note 8: the current comparator output current varies linearly with temperature. note 9: the pwrgd and ovp comparators incorporate 10mv of hysteresis. note 10: the driver disable time-out is proportional to the sync period within the frequency synchronization range. symbol parameter conditions min typ max units v aux v aux auxiliary supply voltage c vaux = 0.1 m f, i load = 0ma to 10ma, v dd = 7v to 12.6v l 3.135 3.320 3.465 v current limit amplifier i isnsgnd i snsgnd input current v isnsgnd = 0v l 0.05 1 m a i isns i sns input current v isns = 0v l 0.05 1 m a v ilimth current limit threshold v icomp = 2.5v, v isnsgnd = 0v C 27.0 C 25 C 23.0 mv (v isns C v isnsgnd ) l C 27.5 C 25 C 22.5 mv i icomp i comp source current v isnsgnd = 0v, v isns = C 0.3v, v icomp = 2.5v (note 8) C 280 C 200 C 120 m a l C 370 C 200 C 80 m a i comp sink current v isnsgnd = 0v, v isns = 0.3v, v icomp = 2.5v (note 8) 120 200 280 m a l 80 200 370 m a g milim current limit amplifier v isnsgnd = 0v, v icomp = 2.5v, i icomp = 10 m a l 2.2 3.5 5 millimho transconductance g icomp current limit amplifier v icomp = 2.5v, no load l 48 60 db open-loop dc gain pwrgd and ovp comparators v pwrgd percent below v fb v fb , margin = open (note 9) l C9 C6 C3 % i pwrgd power good sink current v fb = 2v l 10 m a v fb = 0v l 10 ma v ol power good output low voltage i pwrgd = 3ma, v fb = 0v l 0.4 v v ovpref ovpin threshold v fb = v isns = v isnsgnd = 0v, ovpin - (note 9) l 1.18 1.233 1.28 v i ovpin ovpin input bias current v ovpin = 1.233v l 0.1 1 m a t pwrgd power good response time v fb - l 125 ms power bad response time v fb l 0.5 1 2.5 ms t ovp overvoltage response time v ovpin - , c optodrv = 0.1 m f l 520 m s sync and drivers v pt sync input positive threshold l 1 1.6 2.2 v v nt sync input negative threshold l C 2.2 C1.6 C1 v i sync sync input current v sync = 10v l 150 m a f sync sync frequency range c fg = c cg = 1000pf, v sync = 5v l 50 400 khz t d sync input to driver output delay c fg = c cg = 1000pf, f sync = 100khz, v sync = 5v l 40 90 ns t sync minimum sync pulse width f sync = 100khz, v sync = 10v (note 6) l 75 ns t r , t f driver rise and fall time c fg = c cg = 1000pf, f sync = 100khz, v sync = 5v, l 10 40 ns 10% to 90% t ddis driver disable time-out c fg = c cg = 1000pf, f sync = 100khz, v sync = 5v measured from cg - (note 10) l 10 15 20 m s
4 ltc1698 1698f typical perfor a ce characteristics uw v fb vs temperature temperature ( c) ?0 v fb (v) 1.236 1.242 1.248 25 75 150 1698 g01 1.230 1.224 1.218 ?5 0 50 100 125 v dd = 8v v dd (v) 5 1.218 v fb (v) 1.224 1.236 1.242 1.248 7 9 10 14 1698 g02 1.230 68 11 12 13 t a = 25 c v margin (v) 0 v fb (v) ? v fb (%) 1.245 1.270 1.295 2.64 1698 g03 1.221 1.196 1.233 1.258 1.282 1.208 1.184 1.171 1 3 5 ? ? 0 2 4 ? ? ? 0.66 0.33 1.32 0.99 1.98 2.31 2.97 1.65 3.3 v dd = 8v t a = 25 c v fb vs v dd v fb vs v margin i sns threshold vs temperature i sns threshold vs v dd current limit amplifier g m vs temperature temperature ( c) ?0 27.5 i sns threshold (mv) 27.0 26.0 25.5 25.0 22.5 24.0 0 50 75 1698 g04 26.5 23.5 23.0 24.5 ?5 25 100 125 150 v dd = 8v v dd (v) 5 27.5 i sns threshold (mv) 27.0 26.0 25.5 25.0 22.5 24.0 8 7 10 11 1698 g05 26.5 23.5 23.0 24.5 69 12 13 14 t a = 25 c temperature ( c) ?0 g milim (millimho) 3.8 4.2 4.6 100 125 1698 g06 3.4 3.0 ?5 25 0 50 75 150 2.6 2.2 5.0 v dd = 8v ovpin threshold vs temperature ovpin threshold vs v dd power good threshold vs temperature temperature ( c) ?0 ovpin threshold (v) 1.24 1.26 1.28 25 75 150 1698 g07 1.22 1.20 1.18 ?5 0 50 100 125 v dd = 8v v dd (v) 5 1.18 ovpin threshold (v) 1.20 1.24 1.26 1.28 7 9 10 14 1698 g08 1.22 68 11 12 13 t a = 25 c temperature ( c) ?0 power good threshold (v) ? v fb (%) 1.166 1.181 1.196 25 75 150 1698 g09 1.152 1.137 1.122 5.4 4.2 3.0 6.6 7.8 9.0 ?5 0 50 100 125 v dd = 8v
5 ltc1698 1698f typical perfor a ce characteristics uw v aux vs temperature v aux vs line voltage v aux vs load current v aux short-circuit current vs temperature v aux short-circuit current vs v dd opto driver load regulation opto driver short-circuit current vs temperature temperature ( c) ?0 v aux (v) 3.300 3.383 150 1698 g10 3.218 3.135 0 50 100 ?5 25 75 125 3.465 3.259 3.341 3.176 3.424 v dd = 8v i load = 0ma v dd (v) 5 v aux (v) 3.300 3.383 14 1698 g11 3.218 3.135 78 10 12 6 9 11 13 3.465 3.259 3.341 3.176 3.424 v dd = 8v i load = 0ma load current (ma) 0 v aux (v) 3.300 3.383 10 9 1698 g12 3.218 3.135 23 5 7 1 4 6 8 3.465 3.259 3.341 3.176 3.424 v dd = 8v t a = 25 c temperature ( c) ?0 v aux short-circuit current (ma) ?0 ?0 0 25 75 150 1698 g13 ?0 ?0 ?0 ?5 0 50 100 125 v dd = 8v v dd (v) 5 v aux short-circuit current (ma) ?0 ?0 0 810 14 1698 g14 ?0 ?0 ?0 67 9 11 12 13 t a = 25 c load current (ma) 0 opto driver output voltage (v) percent (%) 3.006 3.018 3.030 8 1698 g15 2.994 2.982 3.000 3.012 3.024 2.988 2.976 2.970 0.2 0.6 1.0 0.2 0.6 0 0.4 0.8 0.4 0.8 ?.0 2 1 4 3 67 9 5 10 v dd = 8v t a = 25 c temperature ( c) ?0 opto driver short-circuit current (ma) ?0 ?0 150 1698 g16 ?0 ?0 0 50 100 ?5 25 75 125 ?0 ?5 ?5 ?5 ?5 v dd = 8v v optodrv = 1.233v maximum opto driver output voltage vs load current maximum opto driver output voltage vs temperature load current (ma) 0 maximum opto driver output voltage (v) 4 6 8 1698 g22 2 0 2 4 5 10 8 6 1 3 9 7 v dd = 10v v dd = 8v v dd = 7v v dd = 6v v dd = 5v t a = 25 c v comp = 0v temperature ( c) ?0 0 maximum opto driver output voltage (v) 2 4 6 8 25 0 25 50 1698 g23 75 100 125 150 v dd = 10v v dd = 8v v dd = 6v v dd = 5v v comp = 0v i optodrv = 10ma v dd = 7v
6 ltc1698 1698f typical perfor a ce characteristics uw i vdd vs sync frequency f sync (khz) 50 i vdd (ma) 30 40 50 450 1698 g19 20 10 25 35 45 15 5 0 150 100 250 200 350 400 300 500 v dd = 8v t a = 25 c c fg = c cg = 4700pf c fg = c cg = 3300pf c fg = c cg = 2200pf c fg = c cg = 1000pf temperature ( c) ?0 sync positive threshold (v) 2.00 2.25 25 75 150 1698 g20 1.75 1.50 1.25 1.00 ?5 0 50 100 125 v dd = 8v v dd (v) 5 1.00 sync positive threshold (v) 1.24 1.72 1.96 2.20 7 9 10 14 1698 g21 1.48 68 11 12 13 t a = 25 c sync positive threshold vs temperature sync positive threshold vs v dd undervoltage lockout threshold vs temperature temperature ( c) ?0 v uvlo (v) 3 4 5 25 75 150 1698 g24 2 1 0 ?5 0 50 100 125 i vdd vs v dd opto driver short-circuit current vs v dd v dd (v) 5 opto driver short-circuit current (ma) ?0 ?0 0 810 14 1698 g17 ?0 ?0 ?0 67 9 11 12 13 t a = 25 c v optodrv = 1.233v v dd (v) 5 i vdd (ma) 12 16 20 13 1698 g18 8 4 10 14 18 6 2 0 7 6 9 8 11 12 10 14 t a = 25 c f sync = 100khz c fg = c cg = 4700pf c fg = c cg = 3300pf c fg = c cg = 2200pf c fg = c cg = 1000pf driver load (pf) 0 time (ns) 4000 8000 10000 90 80 70 60 50 40 30 20 10 0 1698 g25 2000 6000 v dd = 8v t a = 25 c cg, fg t phl t f t r cg, fg t plh temperature ( c) 50 ?5 0 25 50 75 100 125 150 t d (ns) 90 80 70 60 50 40 30 20 10 0 1698 g26 v dd = 8v c cg = c fg = 1000pf f sync = 100khz cg, fg t plh cg, fg t phl f sync (khz) 50 driver disable time-out t diss ( s) 150 250 300 500 1698 g27 100 200 350 400 450 30 25 20 15 10 5 0 normalized driver disable time-out t diss f sync 2.2 2.0 1.8 1.6 1.4 1.2 1.0 v dd = 8v t a = 25 c t diss f sync t diss driver rise, fall and propagation delay vs driver load sync input to driver output delay vs temperature driver disable time-out vs sync frequency
7 ltc1698 1698f uu u pi fu ctio s v dd (pin 1): power supply input. for isolated applica- tions, a simple rectifier from the power transformer is used to power the chip. this pin powers the opto driver, the v aux supply and the fg and cg drivers. an internal 5v regulator powers the remaining circuitry. v dd requires an external 4.7 m f bypass capacitor. cg (pin 2): catch gate driver. if sync slews positive, cg pulls high to drive an external n-channel mosfet. cg draws power from the v dd pin and swings between v dd and pgnd. pgnd (pin 3): power ground. connect pgnd to a low impedance ground plane in close proximity to the ground terminal of the external current sensing resistor. gnd (pin 4): logic and signal ground. gnd is referenced to the internal low power circuitry. careful board layout techniques must be used to prevent corruption of signal ground reference. connect gnd and pgnd together di- rectly at the ltc1698. optodrv (pin 5): optocoupler driver output. this pin drives a ground referenced optocoupler through an exter- nal resistor. if v fb is low, optodrv pulls low. if v fb is high, optodrv pulls high. this optocoupler driver has a dc gain of 5. during overvoltage or overcurrent condi- tions, optodrv pulls high. the output is capable of sourcing 10ma of current and will drive an external 0.1 m f capacitive load and is short-circuit protected. v comp (pin 6): error amplifier output. this error amplifier is able to drive more than 2k w and 100pf of load. the internal diode connected from v fb to v comp reduces optodrv recovery time under start-up conditions. margin (pin 7): current input to adjust the output voltage linearly. the margin pin connects to an internal 16.5k resistor. the other end of this resistor is regulated to 1.65v. connecting margin to a 3.3v logic supply sources 100 m a of current into the chip and moves the output voltage 5% higher. connecting margin to 0v sinks 100 m a out of the pin and moves the regulated output voltage 5% lower. the margin pin voltage does not affect the pwrgd and ovpin trip points. v fb (pin 8): feedback voltage. v fb senses the regulated output voltage through an external resistor divider. the v fb pin is servoed to the reference voltage of 1.233v under closed-loop conditions. an rc network from v fb to v comp compensates the feedback loop. if v fb goes low, v comp pulls high and optodrv goes low. ovpin (pin 9): overvoltage input. ovpin is a high imped- ance input to an internal comparator. the threshold of this comparator is set to 1.233v. if the ovpin potential is higher than the threshold voltage, optodrv pulls high immediately. use an external rc lowpass filter to prevent noisy signals from triggering this comparator. pwrgd (pin 10): power good output. this is an open- drain output. pwrgd floats if v fb is above 94% of the nominal value for more than 2ms. pwrgd pulls low if v fb is below 94% of the nominal value for more than 1ms. the pwrgd threshold is independent of the margin pin potential. i snsgnd (pin 11): current sense ground. connect to the positive side of the sense resistor, normally grounded. i sns (pin 12): current sense input. connect to the nega- tive side of the sense resistor through an external rc lowpass filter. this pin normally sees a negative voltage, which is proportional to the average load current. if current limit is exceeded, optodrv pulls high. i comp (pin 13): current amplifier output. an rc network at this pin compensates the current limit feedback loop. referencing the rc to v out controls output voltage over- shoot on start-up. this pin can float if current limit loop compensation is not required. v aux (pin 14): auxiliary 3.3v logic supply. this pin requires a 0.1 m f or greater bypass capacitor. this auxiliary power supply can power external devices and sources 10ma of current. internal current limiting is provided. sync (pin 15): drivers synchronization input. a negative voltage slew at sync forces fg to pull high and cg to pull low. a positive voltage slew at sync resets the fg pin and cg pulls high. if sync loses its synchronization signal for more than the driver disable time-out interval, both the forward and catch drivers output are forced low. the sync circuit accepts pulse and square wave signals. the mini- mum pulse width is 75ns. the synchronization frequency range is between 50khz to 400khz. fg (pin 16): forward gate driver. if sync slews negative, fg goes high. fg draws power from v dd and swings between v dd and pgnd.
8 ltc1698 1698f block diagra w i-to-v converter r margin 20k r ovp 3k 100k v fb 0.94v ref m pwrgd r ilim 3k m ilim margin 7 sync 15 optodrv 5 5% v ref v ref bandgap sync in v cc v dd v aux 14 + + + err + i lim 25mv + ovp v ref 1698 bd + opto pwrgd 10 ovpin 9 i comp 13 i sns 12 i snsgnd 11 v comp 6 v fb 8 cg 2 fg 16 pwrgd aux gen v cc gen 1 operatio u the ltc1698 is a secondary-side synchronous rectifier controller designed to work with the lt3781 primary-side synchronous controller chip to form an isolated synchro- nous forward converter. this chip set uses a dual transis- tor forward topology that is predominantly used in distrib- uted power supply systems where isolated low voltages are needed to power complex electronic equipment. the primary stage is a current mode, fixed frequency forward converter and provides the typical pwm operation. a power transformer is used to provide the functions of input/output isolation and voltage step-down to achieve the required low output voltage. instead of using typical schottky diodes, synchronous rectification on the sec- ondary offers isolation with high efficiency. it supplies high power without the need of bulky heat sinks, which is often a problem in any space constrained application. the ltc1698 not only provides synchronous drivers for the external mosfets, it comes with other housekeeping functions performed on the secondary side of the power supply, all within a single integrated controller. figure 1 shows the typical chip-set application. upon power up, the ltc1698s v dd input is low, the gate drivers tg and bg are both at the ground potential. the secondary forward and (refer to block diagram)
9 ltc1698 1698f catch mosfets q3 and q4 are off. as soon as transistors q1 and q2 turn on, the flux in the power transformer t1 forces the body diodes of q3 and q4 to conduct, and the whole circuit starts like a conventional forward converter. at the same time, the ltc1698 v dd potential ramps up quickly through the v dd bias circuitry. once the v dd voltage exceeds 4.0v, the ltc1698 enables its drivers and enters synchronous operation. the pulse transformer t2 synchronizes the primary and secondary mosfet drivers. in a typical conversion cycle, the primary mosfets q1 and q2 turn on simultaneously. sg goes low and generates a negative spike at the ltc1698 sync input through the pulse transformer. the ltc1698 forces fg to turn on and cg to turn off. power is delivered to the load through the transformer t1 and the inductor l1. at the beginning of the next phase in which q1 and q2 turn off, sg goes high, sync sees a positive spike, the mosfet q3 shuts off, q4 conducts and allows continuous current to flow through the inductor l1. the capacitor c out filters the switching waveform to provide a steady dc output voltage for the load. the ltc1698 error amplifier err senses the output volt- age through an external resistor divider and regulates the v fb pin potential to the 1.233v internal bandgap voltage. an external rc network across the v fb and v comp pins frequency compensates the error amplifier feedback. the opto driver amplifies the voltage difference between the v comp pin and the bandgap potential, driving the external optocoupler diode with an inverting gain of 5. the optocoupler feeds the amplified output error signal to the primary controller and closes the forward converter volt- age feedback loop. under start-up conditions, the internal diode across the ltc1698 error amplifier clamps the v comp pin. this speeds up the opto driver recovery time by reducing the negative slew rate excursion at the comp pin. the forward converter output voltage can be easily ad- justed. the potential at the margin pin is capable of forcing the error amplifier reference voltage to move linearly by 5%. the internal r margin resistor converts the margin voltage to a current and linearly controls the offset of the error amplifier. connecting the margin pin to 3.3v increases the v fb voltage by 5%, and connecting the margin pin to 0v reduces v fb by 5%. with the margin pin floating, the vfb voltage is regulated to the internal bandgap voltage. the current limit transconductance amplifier i lim provides the secondary side average current limit function. the average voltage drops across the r secsen resistor is sensed and compared to the C 25mv threshold set by the internal i lim amplifier. once i lim detects high output current, the current amplifier output pulls high, overrides the error amplifier, injects more current into the photo diode and forces a lower duty cycle. an rc network connected to the i comp pin is used to stabilize the second- ary current limit loop. alternatively, if only overcurrent fault protection is required, i comp can float. if under abnormal conditions the feedback path is broken, ovpin provides another route for overvoltage fault pro- tection. if the voltage at ovpin is higher than the bandgap voltage, the ovp comparator forces optodrv high im- mediately. a simple external rc filter prevents a momen- tary overshoot at ovpin from triggering the ovp comparator. short ovpin to ground if this pin is not used. the ltc1698 provides an open-drain pwrgd output. if v fb is less than 94% of its nominal value for more than 1ms, the pwrgd comparator pulls the pwrgd pin low. if v fb is higher than 94% of its nominal value for more than 2ms, the transistor m pwrgd shuts off, and an external resistor pulls the pwrgd pin high. the ltc1698 provides an auxiliary 3.3v logic power supply. this auxiliary power supply is externally compen- sated with a minimum 0.1 m f bypass capacitor. it supplies up to 10ma of current to any external devices. operatio u (refer to block diagram)
10 ltc1698 1698f applicatio s i for atio wu uu undervoltage lockout in uvlo (low v dd voltage) the drivers fg and cg are shut off and the pins optodrv, v aux , pwrgd and i comp are forced low. the ltc1698 allows the bandgap and the internal bias currents to reach their steady-state values before releasing uvlo. typically, this happens when v dd reaches approximately 4.0v. beyond this threshold, the drivers start switching. the optodrv, v aux , pwrgd and i comp pins return to their normal values and the chip is fully functional. however, if the v dd voltage is less than 7v, the optodrv and v aux current sourcing capabilities are limited. see the opto driver graphs in the typical perfor- mance characteristics section. v dd regulator the bias supply for the ltc1698 is generated by peak rectifying the isolated transformer secondary winding. as shown in figure 2, the zener diode z1 is connected from base of q5 to ground such that the emitter of q5 is regulated to one diode drop below the zener voltage. r z is selected to bring z1 into conduction and also provide base current to q5. a resistor (on the order of a few hundred ohms), in series with the base of q5, may be required to surpress high frequency oscillations depending on q5s selection. a power mosfet can also be used by increasing the zener diode value to offset the drop of the gate-to- source voltage. v dd supply current varies linearly with the supply voltage, driver load and clock frequency. a 4.7 m f bypass capacitor for the v dd supply is sufficient for most applications. this capacitor must be large enough to provide a stable dc voltage to meet the ltc1698 v dd supply requirement. under start-up conditions, it must be small enough to power up instantaneously, enabling the ltc1698 to regulate the feedback loop. using a larger capacitor requires evaluation of the start-up performance. sync input figure 3 shows the synchronous forward converter appli- cation. the primary controller lt3781 runs at a fixed frequency and controls mosfets q1 and q2. the second- ary controller ltc1698 controls mosfets q3 and q4. an inexpensive, small-size pulse transformer t2 synchro- nizes the primary and the secondary controllers. figure 4 shows the pulse transformer timing waveforms. when the lt3781 synchronization output sg goes low, mosfet v secondary 1 d3 r z 2k r b * *r b is optional, see text z1 10v q5 fzt690 0.47 f 4.7 f 1698 f02 v dd figure 2. v dd regulator d2 t1 t2 v in d1 q1 q2 q3 q4 primary controller lt3781 tg bg sg secondary controller ltc1698 cg l1 c out v out fg sync c sg isolation barrier secondary primary c sync r sync 1698 f03 figure 3. synchronization using pulse transformer tg bg sg sync fg cg 1698 f04 figure 4. primary side and secondary side synchronization waveforms
11 ltc1698 1698f drivers tg and bg go high. the pulse transformer t2 generates a negative slew at the sync pin and forces the secondary mosfet driver fg to go high and cg to go low. when tg and bg go low, sg goes high and the secondary controller forces cg high and fg low. for a given pulse transformer, a bigger capacitor c sg generates a higher and wider sync pulse. the peak of this pulse should be much higher than the sync threshold. amplitudes greater than 5v help to speed up the sync comparator and reduce the sync to fg and cg drivers propagation delay. the minimum pulse width is 75ns. overshoot during the pulse transformer reset interval must be minimized and kept below the minimum com- parator thresholds of 1v. the amount of overshoot can be reduced by having a smaller reset resistor r sync . for nonisolated applications, the sync input can be driven directly by a square pulse. to reduce the propagation delay, make the positive and negative magnitude of the square wave much greater than the 2.2v maximum threshold. in addition to the simple driver synchronization, the sec- ondary controller requires a driver disable signal. loss of synchronization while cg is high will cause q4 to dis- charge the output capacitor. this produces a negative output voltage transient and possible damage to the load circuitry connected to v out . to overcome this problem, the ltc1698 comes with a unique adaptive time-out circuit. it works well within the 50khz to 400khz frequency range. at every positive sync pulse, the internal timer resets. if the sync signal is missing, the internal timer loses its reset command, and eventually exceeds the internal time-out limit. this forces both the fg and cg drivers to go low immediately. the time-out duration varies linearly with the lt3781 primary controller clocking frequency. upon power up, the time-out circuitry takes a few clock cycles to adapt to the input clock frequency. during this time interval, the drivers pulse width might be prematurely terminated, and the inductor current flows through the mosfets body diode. once the ltc1698 timer locks to the clocking frequency, the ltc1698 drivers follow the sync signal without fail. figure 5 shows the sync time-out wave- forms. the time-out circuit guarantees that if the sync pulse is missing for more than one period, both the drivers will be shut down preventing the output voltage from going below ground. the wide synchronization frequency range adds flexibility to the forward converter and allows this converter chip set to meet different application requirements. under normal operating conditions, the time-out circuitry adapts to the switching frequency within a few cycles. once synchronized, internal circuitry ensures the maxi- mum time that the catch fet (q4) could be left turned on is typically just over one switching period. this is particu- larly important with high output voltages that can generate significant negative output inductor currents if the catch fet q4 is left on. poor feedback loop performance includ- ing output voltage overshoot can cause the primary con- troller to interrupt the synchronization pulse train. while this generally is not a problem, it is possible that low frequency interruptions could lead to a time-out period longer than a switching period, limited only by the internal timer clamp (50 m s typical). output voltage programming the switching regulator output voltage is programmed through a resistor feedback network (r1 and r2 in figure 1) connected to v fb . if the output is at its nominal value, the divider output is regulated to the error amplifier threshold of 1.233v. the output voltage is thus set according to the relation: v out = 1.233 ? (1 + r2/r1) applicatio s i for atio wu uu sg sync fg cg reset (internal) disdri (internal) 1698 f05 figure 5. sync time-out waveforms
12 ltc1698 1698f margin adjustment the margin input is used for adjusting the programmed output voltage linearly by varying the current flowing into and out of the pin. forcing 100 m a into the pin moves the output voltage 5% higher. forcing 100 m a out of the pin moves the output voltage 5% lower. with the margin pin floating, the v fb pin is regulated to the bandgap voltage of 1.233v. the margin pin is a high impedance input. it is important to keep this pin away from any noise source like the inductor switching node. any stray signal coupled to the margin pin can affect the switching regulator output voltage. this pin is internally connected to a 16.5k resistor that feeds the i-v converter. the i-v converter output linearly controls the error amplifier offset voltage. the input of the i-v converter is biased at 1.65v. this allows the 100 m a current to be obtained by connecting the margin pin to the v aux 3.3v supply (+ 5%) or gnd (C 5%). for output voltage adjustment smaller than 5%, an external resistor r ext as shown in figure 6 is added in series with the internal resistor to lower the current flowing into or out of the margin pin. the value of r ext is calculated as follow: r required k ext = ? ? ? ? 5 1165 % % . v fb loop causes the error amplifier to drive the optodrv pin low, forcing the primary controller to increase the duty cycle. this causes the output voltage to increase to a dangerously high level. to eliminate this fault condition, the ovp comparator monitors the output voltage with a resistive divider at ovpin. a voltage at ovpin higher than the v ref potential forces the optodrv pin high and reduces the duty cycle, thus preventing the output voltage from increasing further. the ovpin senses the output voltage through a resistor divider network (r4 and r5 in figure 1). the divider is ratioed such that the voltage at ovpin equals 1.233v when the output voltage rises to the overvoltage level. the overvoltage level is set following the relation: v overvoltage = 1.233 ? (1 + r5/r4) the ovp comparator is designed to respond quickly to an overvoltage condition. a small capacitor from ovpin to ground keeps any noise spikes from coupling to the ovp pin. this simple rc filter prevents a momentary overshoot from triggering the ovp comparator. the ovp comparator threshold is independent of the potential at the margin pin. if the ovp function is not used, connect ovpin to ground. power good the pwrgd pin is an open-drain output for power good indication. pwrgd floats if v fb is above 94% of the nominal value for more than 2ms. an external pull-up resistor is required for pwrgd to swing high. pwrgd pulls low if v fb drops below 94% of the nominal value for more than 1ms. the pwrgd threshold is referenced to the 1.233v bandgap voltage, which remains unchanged if the margin pin is exercised. opto feedback and frequency compensation for a forward converter to obtain good load and line regulation, the output voltage must be sensed and com- pared to an accurate reference potential. any error voltage must be amplified and fed back to the supplys control circuitry where the sensed error can be corrected. in an isolated supply, the control circuitry is frequently located on the primary. the output error signal in this type of 7 i-v converter r margin r ext (optional) reduce v fb increase v fb margin 14 bandgap aux gen v dd v aux 3.3v v aux 0.1 f v ref 5% v ref + err v fb v comp 1698 f06 8 6 applicatio s i for atio wu uu figure 6. output voltage adjustment overvoltage function the ovpin is used for overvoltage protection and is designed to protect against an open v fb loop. opening the
13 ltc1698 1698f supply must cross the isolation boundary. coupling this signal requires an element that will withstand the isolation potentials and still transfer the loop error signal. optocouplers are widely used for this function due to their ability to couple dc signals. to properly apply them, a number of factors must be considered. the gain, or current transfer ratio (ctr) through an optocoupler is loosely specified and is a strong function of the input current through the diode. it changes considerably as a function of time (aging) and temperature. the amount of aging accelerates with higher operating current. this variation directly affects the overall loop gain of the sys- tem. to be an effective optical detector, the output transis- tor of the optocoupler must have a large base area to collect the light energy. this gives it a large collector to base capacitance which can introduce a pole into the feedback loop. this pole varies considerably with the current and interacts with the overall loop frequency compensation network. the common collector optocoupler configuration removes the miller effect due to the parasitic capacitance and increases the frequency response. figure 7 shows the optocoupler feedback circuitry using the common collec- tor approach. note that the terms r d , ctr, c de and r p vary from part to part. they also change with bias current. the dominant pole of the opto feedback is due to r f and c f . the feedforward capacitor c k at the optocoupler creates a low frequency zero. this zero should be chosen to provide a phase boost at the loop crossover frequency. the parallel combination of r k and r d form a high frequency pole with c k . for most optocouplers, r d is 50 w at a dc bias of 1ma, and 25 w at a dc bias of 2ma. the ctr term is the small signal ac current transfer ratio. for the qt optoelectron- ics moc207 optocoupler used here, the ac ctr is around 1, even though the dc ctr is much lower when biased at 1ma or 2ma. the first denominator term in the v c /v out equation has been simplified and assumes that c fb <1698 v fb 1698 f07 100k optodrv r k c k moc207 + + v ref lt3781 v fb v cc c f v c r f r1 r e + figure 7. error signal feedback
14 ltc1698 1698f a series rc network can be added in parallel with r2 (figure 7) to provide a zero for the feedback loop fre- quency compensation. the opto driver will drive a capacitive load up to 0.1 m f. for optocouplers with a base pin, switching signal noise can get into this high impedance node. connect a large resis- tor, 1m or 2m between the base and the emitter. this increases the diode current and the overall feedback bandwidth slightly, and decreases the optocoupler gain. when designing the resistor in series with the optocoupler diode, it is important to consider the part to part variations in the current transfer ratio and its reduction over tem- perature and aging. the bigger the biasing current, the faster the aging. the ltc1698 opto driver is designed to source up to 10ma of current and swing between 0.4v to (v dd C 2.5v). this should meet the design consideration of most optocouplers. besides the voltage feedback function, the ltc1698 opto driver couples fault signals to the primary controller and prevents catastrophic damage to the circuit. upon current limit or an overvoltage fault, the i lim or ovp comparator overrides the error amplifier output and forces the optodrv pin high. this sources maximum current into the external optodiode and reduces the forward converter duty cycle. average current limit the secondary current limit function is implemented by measuring the negative voltage across the current sense resistor r secsen . the current limit transconductance amplifier i lim has a C 25mv threshold. as shown in figure 8, if the secondary current is small, the i comp pin goes low and the transistor m ilim shuts off. the potential at v comp determines the optodrv output. if the second- ary current is large, i comp pulls high and forces the tran- sistor m ilim to turn on hard. thus the current limit circuit overrides the voltage feedback and forces optodrv high and injects maximum current into the external optocoupler. the r ilim resistor provides a linear relationship between the current sensed and the optodrv output. the i sns and i snsgnd pins allow a true kelvin current sense measurement and offer true differential measure- ment across the sense resistor. a differential lowpass filter formed by r6 and c2 removes the pulse-to-pulse inductor current ripple and generates the average sec- ondary current which is equal to the load current. the lowpass corner frequency is typically set to 1 to 2 orders of magnitude below the switching frequency and follows the relationship: r mv i r c f secsen lmax sw = = p 25 6 1 22 10 where: r secsen = secondary current sense resistor i lmax = maximum allowed secondary current f sw = forward converter switching frequency applicatio s i for atio wu uu + + 12 11 2 16 opto i lim + optodrv v out r cilm c cilm v ref v comp ltc1698 i snsgnd i sns fg cg drive 25mv 20k 100k m ilim r ilim 3k 5 i comp 13 c2 q4 q3 t1 r secsen 1698 f08 r6 r6 r div (optional) figure 8. secondary average current limit
15 ltc1698 1698f if the application generates a bigger current sense voltage, a potential divider can be easily obtained by adding a resistor across c2. with this additional resistor, the volt- age sensed by the current comparator becomes: r rr v div div rsense + ( ) 26 an rc network formed by r cilm and c cilm between i comp and v out can be used to stabilize the current limit loop. connecting the compensation network to v out minimizes output overshoot during start-up or short-circuit recov- ery. the r cilm and c cilm zero should be chosen to be well within the closed-loop crossover frequency. this pin can be left floating if current loop compensation is not re- quired. the forward converter secondary current limit func- tion can be disabled by shorting i sns and i snsgnd to ground. auxiliary 3.3v logic power supply an internal p-channel ldo (low dropout regulator) pro- duces the 3.3v auxiliary supply that can power external devices or drive the margin pin. this supply can source up to 10ma of current and the current limit is provided internally. the pin requires at least a 0.1 m f bypass capacitor. mosfet selection two logic-level n-channel power mosfets (q3 and q4 in figure 1) are required for most ltc1698 circuits. they are selected based primarily on the on-resistance and body diode considerations. the required mosfet r ds(on) should be determined based on input and output voltage, allow- able power dissipation and maximum required output current. the average inductor (l1) current is equal to the output load current. this current is always flowing through either q3 or q4 with the power dissipation split up according to the duty cycle: dc q v v n n dc q v v n n out in p s out in p s () () 3 41 = = ? ? ? ? where n p /n s is the turns ratio of the transformer t1. the r ds(on) required for a given conduction loss can now be calculated by rearranging the relation p = i 2 r. pirdcq r p idcq pirdcq r p idcq max q max ds on q ds on q max q max max q max ds on q ds on q max q max () () () () () () () () () () () () 3 2 3 3 3 2 4 2 4 4 4 2 3 3 4 4 = t= = t= where i max is the maximum load current and p max is the allowable conduction loss. in a typical 2-transistor forward converter circuit, the duty cycle is less than 50% to prevent the transformer core from saturating. this results in the duty cycle of q4 being greater than that of q3. q4 will dissipate more power due to the higher duty cycle. a lower r ds(on) mosfet can be used for q4. this will slow down the turn-on time of q4 since a lower r ds(on) mosfet will have a larger gate capacitance. the next consideration for the mosfet is the characteris- tic of the body diode. the body diodes conduct during the power-up phase, when the ltc1698 v dd supply is ramp- ing up and the time-out circuit is adapting to the sync input frequency. the cg and fg signals terminate prema- turely and the inductor current flows through the body diodes. the body diodes must be able to take the compa- rable amount of current as the mosfets. most power mosfets have the same current rating for the body diode and the mosfet itself. the ltc1698 cg and fg mosfet drivers will dissipate power. this will increase with higher switching frequency, higher v dd or larger mosfets. to calculate the driver dissipation, the total gate charge qg is used. this param- eter is found on the mosfet manufacturers data sheet. the power dissipated in each ltc1698 mosfet driver is: p driver = qg ? v dd ? f sw where f sw is the switching frequency of the converter. applicatio s i for atio wu uu
16 ltc1698 1698f power transformer selection the forward transformer provides dc isolation and deliv- ers energy from the primary to the secondary. unlike the flyback topology, the transformer in the forward converter is not an energy storage device. as such, ungapped ferrite material is typically used. select a power material rated with low loss at the switching frequency. many core manufacturers have selection guides and application notes for transformer design. a brief overview of the more important design considerations is presented here. for operating frequencies greater than 100khz, the flux in the core is usually limited by core loss, not saturation. it is important to review both criteria when selecting the trans former. the ac operating flux density for core loss is given by: b vdc naf ac in pesw = 10 2 8 where: b ac is the ac operating flux density (gauss) dc is the operating duty cycle a e is the effective cross sectional core area (cm 2 ) f sw is the switching frequency to prevent core saturation during a transient condition, the peak flux density is: b v dc max naf pk in max pesw = () ( ) 10 8 the minimum secondary turns count is: nn vv v dc max s min p out d in min () () ( ) = + where: v out is the secondary output voltage v d is the voltage drop across the rectifier in the secondary v in(min) is the minimum input voltage dc(max) is the maximum duty cycle the core must be sized to provide sufficient window area for the amount of wire and insulation needed. the best performance is achieved by making each winding a single layer evenly distributed across the width of the bobbin. multiple layers may be used to increase the copper area. interleaving the primary and secondary windings will decrease the leakage inductance. in a single-ended forward converter, much of the energy stored in the leakage inductance is dissipated in the primary-side mosfet during turn-off. it is good design practice to sandwich the secondary winding between two primary windings. for the 2-transistor forward converter shown in figure 1, energy stored in the leakage inductance is returned to the input by diodes d1 and d2. with this topology, additional insulation for higher isolation can be used without signifi- cant penalty. for a more detailed discussion on transformer core and winding losses, see application note an19. inductor selection the output inductor in a typical ltc1698 circuit is chosen for inductance value and saturation current rating. the output inductor in a forward converter operates the same as in a buck regulator. the inductance sets the ripple current, which is commonly chosen to be 40% of the full load current. ripple current is set by: i vt l ripple out off max = () where: t dc min f off max sw () () = () 1 and dc(min) is calculated based on the maximum input voltage. dc min n n v v p s out in max () () = applicatio s i for atio wu uu
17 ltc1698 1698f once the value of the inductor has been determined, an inductor with sufficient dc current rating is selected. core saturation must be avoided under all operating conditions. under start-up conditions, the converter sees a short circuit while charging the output capacitor. if the inductor saturates, the peak current will dramatically increase. the current will be limited only by the primary controller minimum on time and the circuit impedances. high efficiency converters generally cannot afford the core loss found in low cost iron powder cores, forcing the use of more expensive ferrite, molypermalloy, or kool m m ? cores. as inductance increases, core loss goes down. increased inductance requires more turns of wire so copper losses will increase. the optimum inductor will have equal core and copper loss. ferrite designs have very low core losses and are preferred at higher switching frequencies. therefore, design goals concentrate on minimizing copper loss and preventing saturation. kool m m is a very good, low-loss powder material with a soft saturation characteristic. molypermalloy is more efficient at higher switching fre- quencies, but is also more expensive. surface mount designs are available from many manufacturers using all of these materials. output capacitor selection the output capacitor selection is primarily determined by the effective series resistance (esr) to minimize voltage ripple. in a forward converter application, the inductor current is constantly flowing to the output capacitor, therefore, the ripple current at the output capacitor is small. the output ripple voltage is approximately given by: v i esr fc ripple ripple sw out ?+ ? ? ? ? 1 8 the output ripple is highest at maximum input voltage since i ripple increases with input voltage. typically, once the esr requirement for c out has been satisfied the capacitance is adequate for filtering and has the required rms current rating. fast load current transitions at the output will appear as a voltage across the esr of the output capacitor until the feedback loop can change the inductor current to match the new load current value. as an example: at 3.3v out, a 10a load step with a 0.01 w esr output capacitor would experience a 100mv step at the output, a 3% output change. in surface mount applications, multiple capaci- tors may have to be placed in parallel to meet the esr requirement. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc1698. these items are also illustrated graphically in figure 9. check the following for your layout: 1. keep the power circuit and the signal circuit segre- gated. place the power circuit, shown in bold, so that the two mosfet drain connections are made directly at the transformer. the two mosfet sources should be as close together as possible. 2. connect pgnd directly to the sense resistor with as short a path as possible. the mosfet gate drive return currents flow through this connection. 3. connect the 4.7 m f ceramic capacitor directly between v dd and pgnd. this supplies the fg and cg drivers and must supply the gate drive current. 4. bypass the v aux supply with a 0.1 m f ceramic capacitor returned to gnd. 5. place all signal components in close proximity to their associated ltc1698 pins. return all signal component grounds directly to the gnd pin. one common connec- tion can be made to v out + from r2, r5 and c cilm . 6. make the connection between gnd and pgnd right at the ltc1698 pins. 7. use a kelvin-sense connection from the i sns and i snsgnd pins to the secondary-side current-limit resistor r secsen . applicatio s i for atio wu uu kool m m is a registered trademark of magnetics, inc.
18 ltc1698 1698f applicatio s i for atio wu uu cg v dd ltc1698 pgnd gnd optodrv v comp margin c fb r1 bold lines indicate high current paths r c c c v fb sync fg v aux i comp i sns i sensgnd pwrgd ovpin 2 1 3 4 5 6 7 8 15 16 c out v out + v out 14 13 12 11 10 9 r2 r7 d3 r secsen q4 c k r k moc207 c4 0.1 f r4 1698 f09 1k 0.1 f 4.7 f t2 t1 0.1 f c cilm r cilm r5 1k + q3 1 l1 figure 9. ltc1698 layout diagram figure 10. simplified single secondary winding 3.3v and 1.8v output isolated dc/dc converter v comp v dd ltc1698 gnd v fb cg fg i sns sync optodrv v cc bias l1 v out1 3.3v at 10a bg lt3781 sg isolation boundary c out2 : poscap, 680 f/4v l2: sumida cep125-ir8mc-h q1, q2: siliconix si7440dp 1698 f10 v in 36v to 72v v ref v c v fb tg gbias 4.7 f cmdsh-3 q1 q2 b340a 3.01k 2.32k l2 1.8 h 0.006 v cc boost cl cl + lt3710 sync tg cset ilcomp ss + 0.1 f 3.3k 33nf 10pf c s 680pf 10k 10k 180pf 0.01 f bgs pgnd sw bg va out v fb 4700pf v out2 1.8v at 10a c out2 + 220
19 ltc1698 1698f figure 11. 36v in -72v in to 5v/30a isolated synchronous forward converter typical applicatio s u v cc 13 2 1 5 1 f 0.01 f 82pf ovlo shdn 1.24k 1% 10k 4.7 f 16v 1000pf 5v ref 6 f set 0.1 f 8 ss 10 12 t2 pulse eng p2033 bas21 bas21 bat54 bat54s zvn3310f 9 v c pgnd 14 v fb 37 4 therm lt3781 sync sgnd 52.3k 1% 10 1k 3k 1k 3.3k fzt690b 0.22 f 50v 1 10k 220pf moc207 1 43 1 4 8 7 5 14 15 8 5 6 7 2 3300pf 2200pf 4700pf 5v ref 5v ref sg 11 sense 15 bg 18 bstref 19 tg 20 bas21 0.1 f 100v 1mh do1608c-105 coilcraft v bst 1.5 f 100v 1.5 f 100v 0.56 h do1813p-561hc 0.022 f 1000pf sync v fb ovpin margin i comp v dd optodrv v aux 0.1 f 16 12 11 i sns i snsgnd fg 2 cg pgnd gnd ltc1698 pwrgd 6 8 9 7 13 1.24k 1% 976 1% 4.22k 1% 3.01k 1% 10 4 3 v comp 1698 f11 mmbz5240b 0.008 1%, 1w 1000pf 100v 2200pf 250v ac t1 pulse pa0285 pulse pa0265 100 10 v in + 36v to 72v v in v out + 5v /30a v out rtn 10 1/4w 1000pf 100v 10 1/4w 330pf + + + + 3.3 v in v in v cc v cc v out v cc v out v cc v in v cc 0 2.43k 1% rt1 100k 1 f on/off v out trim 4.7 f 16v 470 v out fzt853 b0540w 100 0.25w 2k 0.25w 5241b 11v 20k fmmt619 fmmt718 si7456dp si7456dp si7456dp si7884dp si7884dp si7884dp si7884dp si7884dp si7456dp 0.047 f b2100 b2100 470 f 6.3v poscap 470 f 6.3v poscap 470 f 6.3v poscap 470 f 6.3v poscap 22 f 6.3v 1 f 16v 0 b0540w mmbd4148 0 270k 0.25w 73.2k 1% 1 2 3 4 5 7
20 ltc1698 1698f figure 12. lt3781/ltc1698 36v in -72v in to 3.3v/15a isolated synchronous forward converter-quarter brick typical applicatio s u v cc 13 2 1 5 1 f 0.01 f 82pf ovlo shdn 1.24k 1% 10k 270k 1/4w 100 f 20v 1000pf 5v ref 6 f set 4700pf 8 ss 10 bat54 bat54 pulse eng pa0184 bas21 bas21 bat54 zetex zvn3310f 9 v c pgnd 12 v fb 37 4 therm lt3781 sync sgnd 52.3k 1% 10 1k 3k 1k 1k 2k fzt690b 4.7 f 0.22 f 1 10k 5v ref moc207 7 1 43 8 1 5 4 5 14 15 6 5 8 2 3300pf 4700pf 220pf 5v ref 14 sg + 11 sense bg 18 bstref 19 16 17 tg nc nc 15 20 bas21 0.1 f 1mh do1608c-105 coilcraft v bst 3.3 h d01608c-332 coilcraft 0.022 f 1000pf sync v fb ovpin margin i comp v dd optodrv v aux 0.1 f 16 12 11 fg 2 cg pgnd gnd ltc1698 pwrgd 6 8 9 7 13 1.78k 1% 1.24k 1% 3.01k 1% 2.43k 1% 3410 v comp 1698 f12 1k 0.22 f mbr0540 0.03 si7456dp si7456dp 1000pf 100v 1000pf 100v 2200pf 250v murs120 murs120 10 t1 38431 schott 10 mmbt3906 mmbd914 mmbt3906 v in + v in 0.82 f 100v 0.82 f 100v 2 v out + v out 330pf + + + 330 f 6.3v kemet t520 330 f 6.3v kemet t520 330 f 6.3v kemet t520 330 f 6.3v kemet t520 + 3.3 v cc v in v cc v cc 10k 2.43k 1% rt1 100k 0.1 f on/off trim v out + 4.7 10v mmbz5240b 470 + 3.01k 1% 3.01k 1% 3.01k 1% 3.01k 1% 100 1/4w 100 1/4w 9v v out v out + 3 4 2 1 lt1783cs5 +sense ?ense optional differential sense** v cc v in 5v ref fqt7n10l 100 1/4w 100 1/4w 47k 62k 1/4w 4.7 f mmbt3904 optional fast start* v in 18v mmbz5248b 0.1 f 100 9v 5 i sns i snsgnd 0.1 f 1k 1k si7892dp si7892dp si7892dp si7892dp 10 1/4w 10 1/4w r out (optional) 73.2k 1% 3300pf r in (optional) 1 2 3 4 5 6 78
21 ltc1698 1698f typical applicatio s u v cc 14 2 1 5 1 f 25v 82pf ovlo shdn 1.24k 1% 73.2k 1% 24k 10k 270k 0.25w 68 f 25v 1000pf 56k 5v ref 6 f set 4700pf 8 ss 10 13 bat54 bat54 t2 midcom, inc 31264r bas21lt1 bas21lt1 bat54 zvn3310f 9 v c pgnd 12 i max v fb 37 4 therm lt3781 sync sgnd 52.3k 1% 10 1k 3k 1k 3.3k 20k 0.25w 100 0.25w fzt603 zetex 4.7 f 16v 0.22 f 50v 1 10k 5v ref iso1 moc207 7 1 43 3 1 4 6 5 14 15 6 5 8 2 3300pf 4700pf 47 0.01 f 50v 5v ref 15 sg + 11 sense 16 bg 18 bstref 19 tg 17 20 bas21lt1 0.1 f 100v 1mh do1608c-105 coilcraft blksens v bst 220pf 1.5 f 100v 4.7 h do1608c-472 coilcraft 0.022 f 1000pf sync v fb ovpin margin i comp v dd optodrv v aux 0.1 f 50v 0.1 f 50v 16 i sns i snsgnd fg 2 cg pgnd gnd ltc1698 pwrgd 6 8 9 7 13 909 0.1% 8.25k 0.1% 34 11 10 12 v comp 1698 f13 1k 0.01 f murs120t3 0.025 1/2w 3 6 7 5 4 sud40n10-25 sud40n10-25 sud40n10-25 470pf 100v 470pf 100v 2200pf 250v murs120t3 murs120t3 10 1 8 11 12 10 9 2 t1 efd25 10 v in + v in 1.5 f 100v 1.5 f 100v v out + v out 68 f 25v avx 68 f 25v avx 68 f 25v avx 68 f 25v avx 22 0.25w 22 0.25w 25 h mag inc core 55380-a2 18t #18awg 330pf + + + + v top 3.3 v in v cc v in v cc v top v top v out v out + v cc 15v mmbz5245blt1 20k 0.1 f 50v 0.33 f 50v v out + bat54 10 0.25w 10v mmbz5240blt1 10k 1k unless noted: all pnps mmbt39o6lt1 nc 0.015 100pf 200 18v mmbz5248blt1 110 0.1 f t1 efd25-3f3 lp = 120 h 2mil gap each leg 2m polyester film square 0.031 inch margin tape pins 9-10 5t bifilar 33awg pins 2-5 12t bifilar 33awg pins 4-3 7t quadfilar 26awg pins 7,8-11,12 12t bifilar 24awg pins 6-4 8t quadfilar 26awg si4486ey 2 si4486ey 2 215 215 0.033 f figure 13. 36v in -72v in to 12v/5a isolated synchronous forward converter
22 ltc1698 1698f gn16 (ssop) 0502 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .053 ?.068 (1.351 ?1.727) .008 ?.012 (0.203 ?0.305) .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 typ .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) u package descriptio
23 ltc1698 1698f u package descriptio information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. .016 ?.050 (0.406 ?1.270) .010 ?.020 (0.254 ?0.508) 45 0 ?8 typ .008 ?.010 (0.203 ?0.254) 1 n 2 3 4 5 6 7 8 n/2 .150 ?.157 (3.810 ?3.988) note 3 16 15 14 13 .386 ?.394 (9.804 ?10.008) note 3 .228 ?.244 (5.791 ?6.197) 12 11 10 9 s16 0502 .053 ?.069 (1.346 ?1.752) .014 ?.019 (0.355 ?0.483) typ .004 ?.010 (0.101 ?0.254) .050 (1.270) bsc .245 min n 123 n/2 .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) s package 16-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610)
24 ltc1698 1698f ? linear technology corporation 2000 lt/tp 0203 2k ? printed in the usa part number description comments lt1339 high power synchronous dc/dc controller operation up to 60v maximum lt1425 isolated flyback switching regulator general purpose with external application resistor lt1431 programmable reference 0.4% initial voltage tolerance lt1680 high power dc/dc step-up controller operation up to 60v maximum lt1681 dual transistor synchronous forward controller operation up to 72v maximum lt1725 general purpose isolated flyback controller drives external power mosfet with external i sense resistor lt1737 high power isolated flyback controller sense output voltage directly from primary-side winding lt3710 secondary side synchronous post regulator generates a regulated auxiliary output in isolated dc/dc converters, dual n-channel mosfet synchronous drivers lt3781 dual transistor synchronous forward controller operation up to 72v maximum related parts linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com typical applicatio s u lt3781/ltc1698 isolated 3.3v/15a converter lt3781/ltc1698 isolated 3.3v/15a converter load current (a) 0 efficiency (%) 95 90 85 80 75 70 65 5 10 15 20 1698 ta01 25 30 v in = 36v v in = 72v v in = 48v i out (xx) 0 efficiency (%) 95 90 85 80 75 70 12 1698 ta02 3 6 9 15 v in = 36v v in = 72v v in = 48v lt3781/ltc1698 isolated 3.3v/15a converter efficiency vs load current lt3781/ltc1698 isolated 5v/30a converter efficiency vs load current top bottom

▲Up To Search▲

Price & Availability of 1698

	To Download 1698 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .